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cy7c130, cy7c130a cy7c131, cy7c131a 1 k 8 dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06002 rev. *g revised october 11, 2010 1 k 8 dual-port static ram features true dual-ported memory cells, which allow simultaneous reads of the same memory location 1 k 8 organization 0.65 micron cmos for optimum speed and power high speed access: 15 ns low operating power: i cc = 110 ma (maximum) fully asynchronous operation automatic power-down master cy7c130/130a/cy7c131/ 131a easily expands data bus width to 16 or more bits using slave cy7c140/cy7c141 busy output flag on cy7c130/130a/cy7c131/131a; busy input on cy7c140/cy7c141 int flag for port-to-port communication available in 48-pin dip (cy7c130/130a/140), 52-pin plcc, 52-pin tqfp pb-free packages available functional description the cy7c130/130a/cy7c131/131a/cy7c140 [1] and cy7c141 are high speed cmos 1 k by 8 dual-port static rams. two ports are provided permitting independent access to any location in memory. the cy7c130/130a/cy7c131/131a can be used as either a standalone 8-bit dual-por t static ram or as a master dual-port ram in conjunction with the cy7c140/cy7c141 slave dual-port device in systems requiring 16-bit or greater word widths. it is the solution to applications requiring shared or buffered data, such as cache memory for dsp, bit-slice, or multi- processor designs. each port has independent control pins; chip enable (ce ), write enable (r/w ), and output enable (oe ). two flags are provided on each port, busy and int . busy signals that the port is trying to access the same location currently being accessed by the other port. int is an interrupt flag indicating that data is placed in a unique location (3ff for the left port and 3fe for the right port). an automatic power down feature is controlled independently on each port by the chip enable (ce ) pins. the cy7c130/130a and cy7c140 are available in 48-pin dip. the cy7c131/131a and cy7c141 are available in 52-pin plcc, 52-pin pb-free plcc, 52-p in pqfp, and 52-pin pb-free pqfp. r/w l busy l ce l oe l a 9l a 0l a 0r a 9r r/w r ce r oe r ce r oe r ce l oe l r/w l r/w r i/o 7l i/o 0l i/o 7r i/o 0r busy r int l int r arbitration logic (7c130/7c131 only) and interrupt logic control i/o control i/o memory array address decoder address decoder [2] [3] [3] logic block diagram notes 1. cy7c130 and cy7c130a are functionally identical; cy7c131 and cy7c131a are functionally identical. 2. cy7c130/130a/cy7c131/131a (master): busy is open drain output and requires pull-up resistor. cy7c140/cy7c141 (slave): busy is input. 3. open drain outputs: pull-up resistor required. [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 2 of 22 contents pin configurations ........................................................... 3 pin definitions .................................................................. 4 selection guide ................................................................ 4 maximum ratings ............................................................. 5 operating range ............................................................... 5 electrical characteristics ................................................. 5 capacitance ...................................................................... 6 switching characteristics ................................................ 7 switching characteristics ................................................ 9 switching waveforms .................................................... 11 typical dc and ac characteristics .............................. 16 ordering information ...................................................... 17 ordering code definitions ..... .................................... 17 package diagrams .......................................................... 18 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 document history page ................................................. 21 sales, solutions, and legal information ...................... 22 worldwide sales and design s upport ......... .............. 22 products .................................................................... 22 psoc solutions ......................................................... 22 [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 3 of 22 pin configurations figure 1. pin diagram - dip (top view) figure 2. pin diagram - plcc (top view) fig ure 3. pin diagram - pqfp (top view) 13 14 15 16 17 18 19 20 21 22 23 26 27 28 32 31 30 29 33 36 35 34 24 25 gnd 1 2 3 4 5 6 7 8 9 10 11 38 39 40 44 43 42 41 45 48 47 46 12 37 r/w l ce l busy l int l oe l a 0l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l ce r r/w r busy r int r oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 7r i/o 6r i/o 5r i/o 4r i/o 3r i/o 2r i/o 1r i/o 0r v cc 7c130 7c140 1 v cc oe r a 0r 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47 a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 4l 5l 6l 7l 0r 1r 2r 3r 4r 5r 6r nc gnd oe busy int a nc r/w ce r/w busy int nc 0l l l l l l ce r r r r 7c131 7c141 46 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 1415 16 17 18 19 20 21 22 23 24 25 26 52 5150 49 48 47 45 44 43 42 41 40 v cc oe busy int a nc r/w ce r/w busy int nc 0l l l l l l ce r r r r oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 4l 5l 6l 7l 0r 1r 2r 3r 4r 5r 6r nc gnd 7c131 7c141 [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 4 of 22 pin definitions left port right port description ce l ce r chip enable r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 11/12l a 0r ?a 11/12r address i/o 0l ?i/o 15/17l i/o 0r ?i/o 15/17r data bus input/output int l int r interrupt flag busy l busy r busy flag v cc power gnd ground selection guide parameter 7c131-15 [4] 7c131a-15 7c141-15 7c131-25 [4] 7c141-25 7c130-30 7c130a-30 7c131-30 7c140-30 7c141-30 7c130-35 7c131-35 7c140-35 7c141-35 7c130-45 7c131-45 7c140-45 7c141-45 7c130-55 7c131-55 7c140-55 7c141-55 unit maximum access time 15 25 30 35 45 55 ns maximum operating current commercial/ industrial 190 170 170 120 120 110 ma maximum standby current commercial/ industrial 75 65 65 45 45 35 ma shaded areas contain preliminary information. note 4. 15 and 25 ns version available only in plcc/pqfp packages. [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 5 of 22 maximum ratings [5] exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ................................ ?65 ? c to +150 ? c ambient temperature with power applied ..... .............. .............. .......... ?55 ? c to +125 ? c supply voltage to ground potential (pin 48 to pin 24)...........................................?0.5 v to +7.0 v dc voltage applied to outputs in high z state...............................................?0.5 v to +7.0 v dc input voltage ...........................................?3.5 v to +7.0 v output current into outputs (low) .............................. 20 ma static discharge voltage.......................................... > 2001 v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 5 v 10% industrial ?40 ? c to +85 ? c 5 v 10% military [6] ?55 ? c to +125 ? c 5 v 10% electrical characteristics over the operating range [7] parameter description test conditions 7c131-15 [4] 7c131a-15 7c141-15 7c130-30 [4] 7c130a-30 7c131-25,30 7c140-30 7c141-25,30 7c130-35,45 7c131-35,45 7c140-35,45 7c141-35,45 7c130-55 7c131-55 7c140-55 7c141-55 unit min max min max min max min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? 2.4 ? 2.4 ? 2.4 ? v v ol output low voltage i ol = 4.0 ma ? 0.4 ? 0.4 ? 0.4 ? 0.4 v i ol = 16.0 ma [8] ? 0.5 ? 0.5 ? 0.5 ? 0.5 v v ih input high voltage 2.2 ? 2.2 ? 2.2 ? 2.2 ? v v il input low voltage ? 0.8 ? 0.8 ? 0.8 ? 0.8 v i ix input leakage current gnd < v i < v cc ?5 +5 ?5 +5 ?5 +5 ?5 +5 a i oz output leakage current gnd < v o < v cc , output disabled ?5 +5 ?5 +5 ?5 +5 ?5 +5 a i os output short circuit current [9, 10] v cc = max, v out = gnd ? ?350 ? ?350 ? ?350 ? ?350 ma i cc v cc operating supply current ce = v il , outputs open, f = f max [11] commercial ? 190 ? 170 ? 120 ? 110 ma i sb1 standby current both ports, ttl inputs ce l and ce r > v ih , f = f max [11] commercial ? 75 ? 65 ? 45 ? 35 ma i sb2 standby current one port, ttl inputs ce l or ce r > v ih , active port outputs open, f = f max [11] commercial ? 135 ? 115 ? 90 ? 75 ma i sb3 standby current both ports, cmos inputs both ports ce l and ce r > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0 commercial ? 15 ? 15 ? 15 ? 15 ma i sb4 standby current one port, cmos inputs one port ce l or ce r > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, active port outputs open, f = f max [11] commercial ? 125 ? 105 ? 85 ? 70 ma shaded areas contain preliminary information. notes 5. the voltage on any input or i/o pin cann ot exceed the power pin during power up. 6. t a is the ?instant on? case temperature 7. see the last page of this specification for group a subgroup testing information. 8. busy and int pins only. 9. duration of the short circui t should not exceed 30 seconds. 10. this parameter is guaranteed but not tested. 11. at f = f max , address and data inputs are cycling at the maximum frequency of read cycle of 1/t rc and using ac test waveforms input levels of gnd to 3 v. [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 6 of 22 capacitance [10] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 15 pf c out output capacitance 10 pf figure 4. ac test loads and waveforms 3.0 v 5 v output r1 893 ? r2 347 ? 30 pf including jigand scope gnd 90% 90% 10% ? 5ns ? 5 ns 5 v output r1 893 ? r2 347 ? 5pf including jigand scope (a) (b) output 1.40 v equivalent to: thvenin equivalent 5 v 281 ? 30 pf busy or int busy output load (cy7c130/cy7c131 only) 10% all input pulses 250 ? [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 7 of 22 switching characteristics over the operating range [12, 13] parameter description 7c131-15 [14] 7c131a-15 7c141-15 7c130-25 [14] 7c131-25 7c140-25 7c141-25 7c130-30 7c130a-30 7c131-30 7c140-30 7c141-30 unit min max min max min max read cycle t rc read cycle time 15 ?25?30?ns t aa address to data valid [15] ? 15?25?30ns t oha data hold from address change 0 ?0?0?ns t ace ce low to data valid [15] ? 15?25?30ns t doe oe low to data valid [15] ? 10?15?20ns t lzoe oe low to low z [16, 17, 18] 3 ?3?3?ns t hzoe oe high to high z [16, 17, 18] ? 10?15?15ns t lzce ce low to low z [16, 17, 18] 3 ?5?5?ns t hzce ce high to high z [16, 17, 18] ? 10?15?15ns t pu ce low to power-up [16] 0 ?0?0?ns t pd ce high to power-down [16] ? 15?25?25ns write cycle [19] t wc write cycle time 15 ?25?30?ns t sce ce low to write end 12 ?20?25?ns t aw address setup to write end 12 ?20?25?ns t ha address hold from write end 2 ?2?2?ns t sa address setup to write start 0 ?0?0?ns t pwe r/w pulse width 12 ?15?25?ns t sd data setup to write end 10 ?15?15?ns t hd data hold from write end 0 ?0?0?ns t hzwe r/w low to high z [18] ? 10?15?15ns t lzwe r/w high to low z [18] 0 ?0?0?ns shaded areas contain preliminary information. notes 12. see the last page of this specification for group a subgroup testing information. 13. test conditions assume signal transition times of 5 ns or less , timing reference levels of 1.5 v, input pulse levels of 0 to 3.0 v and output loading of the specified i ol /i oh, and 30 pf load capacitance. 14. 15 and 25 ns version available only in plcc/pqfp packages. 15. ac test conditions use v oh = 1.6 v and v ol = 1.4 v. 16. this parameter is guaranteed but not tested. 17. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 18. t lzce , t lzwe , t hzoe , t lzoe , t hzce and t hzwe are tested with c l = 5 pf as in part (b) of ac test loads . transition is measured 500 mv from steady state voltage. 19. the internal write time of the memory is defined by the overlap of cs low and r/w low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold ti ming should be referenced to the rising edge of the signal tha t terminates the write. [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 8 of 22 busy/interrupt timing t bla busy low from address match ? 15?20?20ns t bha busy high from address mismatch [20] ? 15?20?20ns t blc busy low from ce low ? 15?20?20ns t bhc busy high from ce high [20] ? 15?20?20ns t ps port set-up for priority 5 ?5?5?ns t wb [21] r/w low after busy low 0 ?0?0?ns t wh r/w high after busy high 13 ?20?30?ns t bdd busy high to valid data ? 15?25?30ns t ddd write data valid to read data valid ? note 22 ? note 22 ? note 22 ns t wdd write pulse to data delay ? note 22 ? note 22 ? note 22 ns interrupt timing t wins r/w to interrupt set time ? 15?25?25ns t eins ce to interrupt set time ? 15?25?25ns t ins address to interrupt set time ? 15?25?25ns t oinr oe to interrupt reset time [20] ? 15?25?25ns t einr ce to interrupt reset time [20] ? 15?25?25ns t inr address to interrupt reset time [20] ? 15?25?25ns shaded areas contain preliminary information. switching characteristics over the operating range [12, 13] (continued) parameter description 7c131-15 [14] 7c131a-15 7c141-15 7c130-25 [14] 7c131-25 7c140-25 7c141-25 7c130-30 7c130a-30 7c131-30 7c140-30 7c141-30 unit min max min max min max notes 20. these parameters are measured from the input signal ch anging, until the output pin goes to a high-impedance state. 21. cy7c140/cy7c141 only. 22. a write operation on port a, where port a has priority, leaves the data on port b?s outputs undisturbed until one access tim e after one of the following: busy on port b goes high. port b?s address is toggled. ce for port b is toggled. r/w for port b is toggled during valid read. [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 9 of 22 switching characteristics over the operating range [23, 24] parameter description 7c130-35 7c131-35 7c140-35 7c141-35 7c130-45 7c131-45 7c140-45 7c141-45 7c130-55 7c131-55 7c140-55 7c141-55 unit min max min max min max read cycle t rc read cycle time 35 ? 45 ? 55 ? ns t aa address to data valid [25] ? 35 ? 45?55ns t oha data hold from address change 0 ? 0 ? 0 ? ns t ace ce low to data valid [25] ? 35 ? 45?55ns t doe oe low to data valid [25] ? 20 ? 25?25ns t lzoe oe low to low z [26, 27, 28] 3 ? 3 ?3?ns t hzoe oe high to high z [26, 27, 28] ? 20 ? 20?25ns t lzce ce low to low z [26, 27, 28] 5 ? 5 ?5?ns t hzce ce high to high z [26, 27, 28] ? 20 ? 20?25ns t pu ce low to power-up [26] 0 ? 0 ?0?ns t pd ce high to power-down [26] ? 35 ? 35?35ns write cycle [29] t wc write cycle time 35 ? 45 ? 55 ? ns t sce ce low to write end 30 ? 35 ? 40 ? ns t aw address set-up to write end 30 ? 35 ? 40 ? ns t ha address hold from write end 2 ? 2 ? 2 ? ns t sa address set-up to write start 0 ? 0 ? 0 ? ns t pwe r/w pulse width 25 ? 30 ? 30 ? ns t sd data set-up to write end 15 ? 20 ? 20 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe r/w low to high z [28] ? 20 ? 20?25ns t lzwe r/w high to low z [28] 0 ? 0 ?0?ns notes 23. see the last page of this specification for group a subgroup testing information. 24. test conditions assume signal transition times of 5 ns or less , timing reference levels of 1.5 v, input pulse levels of 0 to 3.0 v and output loading of the specified i ol /i oh, and 30 pf load capacitance. 25. ac test conditions use v oh = 1.6 v and v ol = 1.4 v. 26. this parameter is guaranteed but not tested. 27. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 28. t lzce , t lzwe , t hzoe , t lzoe , t hzce and t hzwe are tested with c l = 5 pf as in part (b) of ac test loads . transition is measured 500 mv from steady state voltage. 29. the internal write time of the memory is defined by the overlap of cs low and r/w low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold ti ming should be referenced to the rising edge of the signal tha t terminates the write. [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 10 of 22 busy/interrupt timing t bla busy low from address match ? 20 ? 25 ? 30 ns t bha busy high from address mismatch [30] ? 20 ? 25?30ns t blc busy low from ce low ? 20 ? 25 ? 30 ns t bhc busy high from ce high [30] ? 20 ? 25?30ns t ps port set-up for priority 5 ? 5 ? 5 ? ns t wb [31] r/w low after busy low 0 ? 0 ? 0 ? ns t wh r/w high after busy high 30 ? 35 ? 35 ? ns t bdd busy high to valid data ? 35 ? 45 ? 45 ns t ddd write data valid to read data valid ? note 32 ? note 32 ? note 32 ns t wdd write pulse to data delay ? note 32 ? note 32 ? note 32 ns interrupt timing t wins r/w to interrupt set time ? 25 ? 35 ? 45 ns t eins ce to interrupt set time ? 25 ? 35 ? 45 ns t ins address to interrupt set time ? 25 ? 35 ? 45 ns t oinr oe to interrupt reset time [20] ? 25 ? 35?45ns t einr ce to interrupt reset time [20] ? 25 ? 35?45ns t inr address to interrupt reset time [20] ? 25 ? 35?45ns switching characteristics over the operating range [23, 24] (continued) parameter description 7c130-35 7c131-35 7c140-35 7c141-35 7c130-45 7c131-45 7c140-45 7c141-45 7c130-55 7c131-55 7c140-55 7c141-55 unit min max min max min max notes 30. these parameters are measured from the input signal ch anging, until the output pin goes to a high-impedance state. 31. cy7c140/cy7c141 only. 32. a write operation on port a, where port a has priority, leaves the data on port b?s outputs undisturbed until one access tim e after one of the following: busy on port b goes high. port b?s address is toggled. ce for port b is toggled. r/w for port b is toggled during valid read. [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 11 of 22 switching waveforms figure 5. read cycle no. 1 [33, 34] figure 6. read cycle no. 2 [33, 35] figure 7. read cycle no. 3 [34] notes 33. r/w is high for read cycle. 34. device is continuously selected, ce = v il and oe = v il . 35. address valid prior to or coincident with ce transition low. t rc t aa t oha data valid previous data valid data out address either port address access t ace t lzoe t doe t hzoe t hzce data valid data out ce oe t lzce t pu i cc i sb t pd either port ce /oe access t bha t bdd valid t ddd t wdd address match address match r/w r address r d inr address l busy l dout l t ps t bla read with busy , master: cy7c130 and cy7c131 t rc t pwe valid t hd [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 12 of 22 figure 8. write cycle no. 1 (oe three-states data i/os?either port [36, 37] figure 9. write cycle no. 2 (r/w three-states data i/os?either port) [38, 39] switching waveforms (continued) t aw t wc data valid high impedance t sce t sa t pwe t hd t sd t ha ce r/w address t hzoe oe d out data in either port t aw t wc t sce t sa t pwe t hd t sd t hzwe t ha high impedance data valid t lzwe address ce r/w data out data in notes 36. the internal write time of the memory is defined by the overlap of cs low and r/w low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold ti ming should be referenced to the rising edge of the signal tha t terminates the write. 37. if oe is low during a r/w controlled write cycle, the write pul se width must be the larger of t pwe or t hzwe + t sd to allow the data i/o pins to enter high impedance and for data to be placed on the bus for the required t sd . 38. these parameters are measured from the input signal ch anging, until the output pin goes to a high-impedance state. 39. if the ce low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high impedance state. [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 13 of 22 figure 10. busy timing diagram no. 1 (ce arbitration) figure 11. busy timing diagram no. 2 (address arbitration) switching waveforms (continued) address match t ps ce l valid first: t blc t bhc address match t ps t blc t bhc address l, r busy r ce l ce r busy l ce r ce l address l,r ce r valid first: left address valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 14 of 22 figure 12. busy timing diagram no. 3 switching waveforms (continued) t pwe t wb t wh write with busy (slave:cy7c140/cy7c141) busy r/w ce [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 15 of 22 figure 13. interrupt timing diagrams switching waveforms (continued) write 3ff t ins t wc t eins right side clears int r t ha t sa t wins read 3ff t rc t einr t ha t int t oinr write 3fe t ins t wc t eins t ha t sa t wins right side sets int l left side sets int r left side clears int l read 3fe t einr t ha t inr t oinr t rc addr r ce l r/w l int l oe l addr r r/w r ce r int l addr r ce r r/w r int r oe r addr l r/w l ce l int r [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 16 of 22 typical dc and ac characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 ?55 25 125 1.2 1.0 120 100 80 60 40 20 0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized supply current vs. ambient temperature ambient temperature ( ? c) output voltage (v) output source current vs. output voltage 0.0 0.8 0.8 0.6 0.6 normalized i cc , i sb v cc = 5.0v v in = 5.0v v cc = 5.0v t a = 25 ? c ? 0 i cc 1.6 1.4 1.2 1.0 0.8 ?55 125 normalized t aa normalized access time vs. ambient temperature ambient temperature ( ? c) 1.4 1.3 1.2 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage 0.6 0.8 1.25 1.0 0.75 10 40 normalized i cc 0.50 normalized i cc vs. cycle time cycle frequency (mhz) 3.0 2.5 2.0 1.5 0.5 0 1.0 2.0 3.0 5.0 normalized t pc 25.0 30.0 20.0 10.0 5.0 0 200 400 600 800 delta t aa (ns) 0 15.0 0.0 supply voltage (v) typical power-on current vs. supply voltage capacitance (pf) typical access time change vs. output loading 4.0 1000 1.0 20 30 0.2 0.6 1.2 i sb3 0.2 0.4 25 1.1 v cc = 4.5v v in = 0.5v normalized i cc , i sb i cc i sb3 t a = 25 ? c ? v cc = 5.0v v cc = 5.0v t a = 25 ? c ? t a = 25 ? c ? v cc = 4.5v v cc = 4.5v t a = 25 ? c ? [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 17 of 22 ordering information speed (ns) ordering code package name package type operating range 55 cy7c130-55pc p25 48-pin (600 mil) molded dip commercial 15 cy7c131a-15jxi j69 52-pin pb-free plastic leaded chip carrier industrial cy7c131-15nxi n52 52-pin pb-free plastic quad flatpack 25 cy7c131-25jxc j69 52-pin pb-free plastic leaded chip carrier commercial cy7c131-25nc n52 52-pin plastic quad flatpack cy7c131-25nxc n52 52-pin pb-free plastic quad flatpack 55 cy7c131-55jxc j69 52-pin pb-free plastic leaded chip carrier commercial cy7c131-55nxc n52 52-pin pb-free plastic quad flatpack CY7C131-55JXI j69 52-pin pb-free plastic leaded chip carrier industrial cy7c131-55nxi n52 52-pin pb-free plastic quad flatpack ordering code definitions temperature range: x = c or i c = commercial; i = industrial xx = p or jx or nx or n p = 48-pin molded dip jx = 52-pin plastic leaded chip carrier (pb-free) nx = 52-pin plastic quad flatpack (pb-free) n = 52-pin plastic quad flatpack xx = speed = 55 or 15 or 25 ns 13xx = 131 or 131a = part number identifier cy7c = cypress srams 13xx cy7c - xx xx x [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 18 of 22 package diagrams figure 14. 48-pin (600 mil) sidebraze dip d26 figure 15. 52-pin pb-free plastic leaded chip carrier j69 51-80044 *a 51-85004 *b [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 19 of 22 figure 16. 48-pin (600 mil) molded dip p25 figure 17. 52-pin pb-free plastic quad flatpack n52 package diagrams (continued) 51-85020 *c 51-85042 *a [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 20 of 22 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor dip dual in-line package i/o input/output oe output enable plcc plastic leaded chip carrier pqfp plastic quad flat pack sram static random access memory tqfp thin quad flat pack ttl transistor?transistor logic symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes ms milli seconds mv milli volts mhz mega hertz pf pico farad wwatts c degree celcius [+] feedback
cy7c130, cy7c130a cy7c131, cy7c131a document number: 38-06002 rev. *g page 21 of 22 document history page document title: cy7c130/cy7c130a/cy7c1 31/cy7c131a 1k x 8 dual-port static ram document number: 38-06002 rev. ecn no. orig. of change submission date description of change ** 110169 szv 09/29/01 change from spec number: 38-00027 to 38-06002 *a 122255 rbi 12/26/02 power up requirements added to maximum ratings information *b 236751 ydt see ecn removed cross information from features section *c 325936 ruy see ecn added pin definitions table, 52-pin pqfp package diagram and pb-free information *d 393153 yim see ecn added cy7c131-15ji to ordering information added pb-free parts to ordering information: cy7c131-15jxi *e 2623540 vkn/pyrs 12/17/08 added cy7c130a and cy7c131a parts removed milita ry information updated ordering information table *f 2897217 rame 03/22/2010 updated ordering information updated package diagrams *g 3054633 admu 10/11/2010 updated ordering information and added ordering code definitions . updated package diagrams . added acronyms and units of measure . minor edits and updated in new template. [+] feedback
document number: 38-06002 rev. *g revised october 11, 2010 page 22 of 22 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c130, cy7c130a cy7c131, cy7c131a ? cypress semiconductor corporation, 2001-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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